The AM4 platform relies on a Pin Grid Array (PGA) architecture. Unlike Intel’s Land Grid Array (LGA) sockets where the pins sit on the motherboard, AMD's PGA design places the fragile pins directly on the bottom of the processor. The Architecture of the AM4 Grid
| Signal Group | Full Name / Function | Key Related Pins/Signals (Examples) | | :--- | :--- | :--- | | | Distributes operating voltage (VDD) and provides the electrical return path (VSS/Ground) to the processor. These are among the most numerous pins. | VDD , VSS | | 🧠 DRAM Memory Interface (DDR4) | Connects to the system's DDR4 memory modules via two independent channels (Channel A and Channel B), supporting functions like addressing, data transfer, and error checking. | MA/MB_ACT_L , MA/MB_ADD[13:0] , MA/MB_DATA[63:0] , MA/MB_ALERT_L , MA/MB_CHECK[7:0] , MA/MB_CKE[1:0] , MA/MB_CS_L[1:0] , MA/MB_ODT[1:0] , MA/MB_CLK_H/L[3:0] | | 🎮 PCI Express (PCIe) Graphics | A dedicated 16-lane PCIe interface for a discrete graphics card. This is a high-speed differential pair interface used for data transmission to and from the GPU. | P_GFX_TXP/TXN[15:0] , P_GFX_RXP/RXN[15:0] | | ⚙️ PCI Express (PCIe) General Purpose | Additional PCIe lanes (typically x4) for general-purpose devices like NVMe SSDs, network cards, or other high-bandwidth peripherals. | P_GPP_TXP/TXN[3:0] , P_GPP_RXP/RXN[3:0] | | 🌉 PCI Express (PCIe) Chipset/Hub | A dedicated PCIe link (typically x4) to the motherboard's chipset (e.g., X570, B550, A320). The chipset then provides additional I/O capabilities (more USB, SATA, etc.). | P_HUB_TXP/TXN[3:0] , P_HUB_RXP/RXN[3:0] | | 🔌 Miscellaneous I/O | A collection of legacy and auxiliary interfaces, including SATA, USB, and general-purpose LPC (Low Pin Count) bus for legacy devices. | SATA_RX(0-1)P/N , SATA_TX , USB0/1/2 , LPC_AD[3:0] , LPC_FRAME_L | | 🔧 System Management & Clocks | Pins dedicated to system clocks (reference and differential clocks for PCIe), power management, and platform security features. | PCIE_RST_L , P0A/P0B_ZVSS , P_ZVDDP , SPI_* signals for BIOS, SMU_* for power management, JTAG_* for debugging | am4 pinout diagram
While this article provides a structured map, you may need a visual reference. Search for: The AM4 platform relies on a Pin Grid
Dedicated links for high-definition audio codecs and direct-to-CPU USB ports. 5. Control, Thermal, and Clock Signals These are among the most numerous pins
A significant portion of the 1331 pins is dedicated to power delivery. These pins ensure the CPU receives a stable voltage. Ground (VSS) pins are interspersed throughout the grid to reduce electrical noise and provide a return path for current.
Rows are labeled A through AR (alphabetically), Columns are 1 through 28. The pinout is asymmetrical.
Pin positions are indexed using letters for rows (A, B, C... avoiding confusing letters like I and O) and numbers for columns (1 to 39).